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IBM Grows Nanotube Patterns On Silicon Wafers
By R. Colin Johnson
EE Times

YORKTOWN HEIGHTS, N.Y. -- IBM Corp. has grown catalyst-free nanotube networks on silicon carbide substrates, the company said last week.

With atomic-force microscopy verifying the results, researchers at the T.J. Watson Research Center set up grids of nanotubes (in rows and columns), bringing the promise of nanotube transistors arrayed across silicon chips one step closer to reality, IBM said.

IBM also announced a patent for its "cookbook" that shows how to grow the pure, catalyst-free nanotubes needed in electronics manufacturing, as opposed to the bulk nanotubes that other suppliers are offering for sale today. Commercially available nanotubes are contaminated by the metallic catalysts used to create the seeds from which they are grown, and vendors damage them if they try to remove the contaminant, according to IBM.

"We have shown that pure, catalyst-free nanotubes that follow the atomic structure of a surface can be grown," said Phaedon Avouris, manager of nanoscale science at IBM Research. "Using atomic-force microscopy, we also showed that at high temperatures they can be moved on the surface, and that [when they cool] they become stabilized in directions that are parallel and perpendicular to the [wafer's patterned] step edges.

Methodology established

"We didn't want to grow our own nanotubes, but we were unhappy with the metallic contamination in the nanotubes we buy from others," Avouris went on. "So we went into the lab to find a way to grow nanotubes without metal catalysts--now we hope that outside suppliers will use our method. We don't really want to be a nanotube manufacturer--we just want some catalyst-free nanotubes for our electronic applications."

During its experiments to create the pure, catalyst-free nanotubes, IBM discovered as a bonus that medium-temperature annealing caused them to align themselves along the step edges in either a perpendicular or a parallel fashion --resulting in square grids of nanotubes spaced at a pitch determined by the patterns on the wafer.

"Of course, there is still much research to be done, but we now believe that by using a patterned silicon substrate, we can generate a specific surface arrangement of nanotubes, and this is just what we need for our electronic applications," Avouris said.

IBM Research is now patterning silicon wafers that enable nanotubes to line up precisely. Using traditional lithography on subsequent layers will allow the nanotubes to form the basis of future ultradense circuits, the company said.