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Stacked, Packed Nanowires Hold Triplexed Megadata

Scientists have created a novel transistor architecture using molecular-scale nanowire memory cells. It promises unprecedently compact data storage.

A novel transistor architecture using molecular-scale nanowire memory cells holds the promise of unprecedently compact data storage.

Researchers at the University of Southern California and the NASA Ames Research Center have successfully tested a self-assembled molecular memory device they say has the potential of holding 40 Gigabits per square centimeter -- a far greater density than any achieved on silicon.

Furthermore, says Chongwu Zhou, an assistant professor in the USC Viterbi School department of electrical engineering, because of the self-assembly feature, such ultra dense memory devices can likely be cheaper than the silicon flash memories now widely used in digital cameras, "memory sticks" and other applications.

According to a recent paper by Zhou and his group in Applied Physics Letters describing the technology, the density is achieved by the nanoscale (one millionth of a millimeter) size of the building blocks used,

The USC/Ames system is still more compact because each memory cell can hold not just one bit of data but three, by virtue of having 8 separate, stable identifiable electronic states.

The USC/Ames system is already quite stable, holding information up to 600 hours. "We believe further work can increase the stability still further," the scientist said.

The USC/Ames researchers synthesized nanowires of indium oxide (In2O3) 10 nanometers in diameter and about 2000 nanometers long, by a "laser ablation" process that first vaporizes an indium containing compound, and then precipitates the indium out in a catalyzed process in which the wires form spontaneously as the indium reacts with ambient oxygen.

The researchers then placed the nanowires on a thin layer of quartz, and activated them by simply submerging them in a solutions of redox materials -- various were tested -- which self-assembled a layer of coating onto the wires, creating transistors.

The resulting transistors could be placed not in one activated state, but three distinct ones, by using different voltages to stimulate them. "We repeated tens of cycles for the endurance test for each memory operation and found that all the levels were distinguishable in the tested cycles," the authors wrote in their APL paper.

In the same paper, they also noted that the assembly process -- a cold one -- "represents a significant departure from the channel hot electron injection commonly used for silicon flash memory," The paper claims that the USC/Ames process requires lower power and is inherently less likely to introduce defects that can cause errors in the device.

The team included, besides Zhou, USC Viterbi School of Engineering graduate students Chao Li, Bo Lei, Daihua Zhang, Son Han, Tao Tang, Xialei Lu, and Zuqin Liu; and Wendy Fan, Sylvia Asano, Jie Han, and Meyya Meyyappan of Ames. Fan, Asano, and Han's contributions were underwritten by the Eloret Corporation, a Sunnyvale CA consulting firm working under contract to NASA.

Source: EurekAlert